15.1 Processors, Parallel Processing & VMs
A Level · 3 questions found
What this topic covers
Section titled “What this topic covers”- RISC vs CISC: differences, interrupt handling on each
- Pipelining and registers in RISC processors
- Four computer architectures: SISD, SIMD, MISD, MIMD
- Characteristics of massively parallel computers
- Virtual machines: concept, roles, benefits and limitations
Past paper questions
Section titled “Past paper questions” Q11
11 Reduced Instruction Set Computers (RISC) and Complex Instruction Set Computers (CISC) are
two types of processor.
(a) State two features of RISC processors.
............................................................................................................................................. [2]
(b) Outline the process of interrupt handling as it could be applied to RISC or CISC processors.
............................................................................................................................................. [3]
(c) Explain how pipelining affects interrupt handling for RISC processors.
............................................................................................................................................. [3]
Permission to reproduce items where third-party owned material protected by copyright is included has been sought and cleared where possible. Every
reasonable effort has been made by the publisher (UCLES) to trace copyright holders, but if any items requiring clearance have unwittingly been included, the
publisher will be pleased to make amends at the earliest possible opportunity.
To avoid the issue of disclosure of answer-related information to candidates, all copyright acknowledgements are reproduced online in the Cambridge
Assessment International Education Copyright Acknowledgements Booklet. This is produced for each series of examinations and is freely available to download
at www.cambridgeinternational.org after the live examination series.
Cambridge Assessment International Education is part of Cambridge Assessment. Cambridge Assessment is the brand name of the University of Cambridge
BLANK PAGE
Show mark scheme
11(a) [2 marks]
mark per mark point (
Max 2
)
Uses
hard-wired code/control units
Uses relatively few instructions / simple instructions
Uses relatively few addressing modes
Makes use of a single-cycle for each instruction
Makes use of fixed length / fixed format instructions
Makes use of general-purpose registers
Pipelining is
straightforward to apply
The design emphasis is on the
software
Processor chips require few transistors.
Max 2
)
Uses
hard-wired code/control units
Uses relatively few instructions / simple instructions
Uses relatively few addressing modes
Makes use of a single-cycle for each instruction
Makes use of fixed length / fixed format instructions
Makes use of general-purpose registers
Pipelining is
straightforward to apply
The design emphasis is on the
software
Processor chips require few transistors.
11(b) [3 marks]
mark per mark point (
Max 3
)
Once the processor detects an interrupt at the start/end of the fetch-execute cycle
… the current program is temporarily stopped and the
status of each register
stored on the stack.
After the interrupt has been serviced/the Interrupt Service Routine (ISR) has been executed …
… the
registers
can be restored to its original status before the interrupt was detected // … the data can be
restored
from the stack
.
Max 3
)
Once the processor detects an interrupt at the start/end of the fetch-execute cycle
… the current program is temporarily stopped and the
status of each register
stored on the stack.
After the interrupt has been serviced/the Interrupt Service Routine (ISR) has been executed …
… the
registers
can be restored to its original status before the interrupt was detected // … the data can be
restored
from the stack
.
11(c) [3 marks]
mark per mark point (
Max 3
)
Pipelining adds an additional complexity // there could be a number of instructions still in the pipeline when the
interrupt is received
All the instructions currently in operation are usually discarded except for the last one/the one at write back
… the interrupt handler routine is applied to the remaining instruction.
Once the interrupt has been serviced the processor can restart with the next instruction in the sequence.
Max 3
)
Pipelining adds an additional complexity // there could be a number of instructions still in the pipeline when the
interrupt is received
All the instructions currently in operation are usually discarded except for the last one/the one at write back
… the interrupt handler routine is applied to the remaining instruction.
Once the interrupt has been serviced the processor can restart with the next instruction in the sequence.
Q9
9
(a) Outline two benefits and two limitations of a virtual machine.
Benefit 1 ...................................................................................................................................
Benefit 2 ...................................................................................................................................
Limitation 1 ...............................................................................................................................
Limitation 2 ...............................................................................................................................
[4]
(b) Explain the roles of the host operating system and the guest operating system as used in a
computer system running a virtual machine.
............................................................................................................................................. [3]
Show mark scheme
9(a) [4 marks]
mark per mark point for up to
two
benefits (
Max 2
)
COMPATIBILTY e.g. Applications that aren’t compatible with the host computer can be run on the virtual machine
// It is possible to emulate old software on a new system by running a compatible guest operating system as a
virtual machine // Software can be tried on different OS on the same hardware.
PROTECTION e.g. The guest operating system has no effect on anything outside the virtual machine other virtual
machines or the host computer//Virtual machines are useful for testing as they will not crash the host computer if
something goes wrong // Easier to recover if software causes a system crash as virtual machine software protects
the host system.
COST e.g. No need to buy extra computers / hardware as multiple virtual machines can be implemented on the
same hardware.
mark per mark point for up to
two
limitations (
Max 2
)
PERFORMANCE e.g. The performance of the guest operating system will not be as good on a virtual machine as
it would be on its own compatible machine because of the extra code / using more RAM/memory space // The
performance of the VM is dependent on the capabilities of the host computer // Response times cannot be
accurately measured using a virtual machine.
COMPLEXITY e.g. Building an in-house virtual machine can be expensive, time consuming and complex to
maintain / set-up.
HARDWARE/SOFTWARE ISSUES e.g. Some hardware/software can’t be emulated with a virtual machine //
Some of the host machine’s hardware can’t be directly accessed by the virtual machine.
two
benefits (
Max 2
)
COMPATIBILTY e.g. Applications that aren’t compatible with the host computer can be run on the virtual machine
// It is possible to emulate old software on a new system by running a compatible guest operating system as a
virtual machine // Software can be tried on different OS on the same hardware.
PROTECTION e.g. The guest operating system has no effect on anything outside the virtual machine other virtual
machines or the host computer//Virtual machines are useful for testing as they will not crash the host computer if
something goes wrong // Easier to recover if software causes a system crash as virtual machine software protects
the host system.
COST e.g. No need to buy extra computers / hardware as multiple virtual machines can be implemented on the
same hardware.
mark per mark point for up to
two
limitations (
Max 2
)
PERFORMANCE e.g. The performance of the guest operating system will not be as good on a virtual machine as
it would be on its own compatible machine because of the extra code / using more RAM/memory space // The
performance of the VM is dependent on the capabilities of the host computer // Response times cannot be
accurately measured using a virtual machine.
COMPLEXITY e.g. Building an in-house virtual machine can be expensive, time consuming and complex to
maintain / set-up.
HARDWARE/SOFTWARE ISSUES e.g. Some hardware/software can’t be emulated with a virtual machine //
Some of the host machine’s hardware can’t be directly accessed by the virtual machine.
9(b) [3 marks]
mark per mark point – host operating system (
Max 2
)
The host operating system is the normal operating system for the host computer / machine.
It has control of all the resources of the host computer / machine. // It can access the physical resources of the
host computer / machine.
It provides a user interface to operate the virtual machine software.
It also runs the virtual machine software.
mark per mark point – guest operating system (
Max 2
)
The guest operating system
runs
within the virtual machine.
… it controls the virtual hardware/software during the emulation. // It accesses the actual hardware through the
virtual machine and host operating system.
It provides a virtual user interface for the emulated hardware/software.
The guest operating system runs under the control of the host operating system.
Max 2
)
The host operating system is the normal operating system for the host computer / machine.
It has control of all the resources of the host computer / machine. // It can access the physical resources of the
host computer / machine.
It provides a user interface to operate the virtual machine software.
It also runs the virtual machine software.
mark per mark point – guest operating system (
Max 2
)
The guest operating system
runs
within the virtual machine.
… it controls the virtual hardware/software during the emulation. // It accesses the actual hardware through the
virtual machine and host operating system.
It provides a virtual user interface for the emulated hardware/software.
The guest operating system runs under the control of the host operating system.
Q11
11 Reduced Instruction Set Computers (RISC) and Complex Instruction Set Computers (CISC) are
two types of processor.
(a) State two features of RISC processors.
............................................................................................................................................. [2]
(b) Outline the process of interrupt handling as it could be applied to RISC or CISC processors.
............................................................................................................................................. [3]
(c) Explain how pipelining affects interrupt handling for RISC processors.
............................................................................................................................................. [3]
Permission to reproduce items where third-party owned material protected by copyright is included has been sought and cleared where possible. Every
reasonable effort has been made by the publisher (UCLES) to trace copyright holders, but if any items requiring clearance have unwittingly been included, the
publisher will be pleased to make amends at the earliest possible opportunity.
To avoid the issue of disclosure of answer-related information to candidates, all copyright acknowledgements are reproduced online in the Cambridge
Assessment International Education Copyright Acknowledgements Booklet. This is produced for each series of examinations and is freely available to download
at www.cambridgeinternational.org after the live examination series.
BLANK PAGE
,
,
Show mark scheme
11(a) [2 marks]
mark per mark point (
Max 2
)
Uses
hard-wired code/control units
Uses relatively few instructions / simple instructions
Uses relatively few addressing modes
Makes use of a single-cycle for each instruction
Makes use of fixed length / fixed format instructions
Makes use of general-purpose registers
Pipelining is
straightforward to apply
The design emphasis is on the
software
Processor chips require few transistors.
Max 2
)
Uses
hard-wired code/control units
Uses relatively few instructions / simple instructions
Uses relatively few addressing modes
Makes use of a single-cycle for each instruction
Makes use of fixed length / fixed format instructions
Makes use of general-purpose registers
Pipelining is
straightforward to apply
The design emphasis is on the
software
Processor chips require few transistors.
11(b) [3 marks]
mark per mark point (
Max 3
)
Once the processor detects an interrupt at the start/end of the fetch-execute cycle
… the current program is temporarily stopped and the
status of each register
stored on the stack.
After the interrupt has been serviced/the Interrupt Service Routine (ISR) has been executed …
… the
registers
can be restored to its original status before the interrupt was detected // … the data can be
restored
from the stack
.
Max 3
)
Once the processor detects an interrupt at the start/end of the fetch-execute cycle
… the current program is temporarily stopped and the
status of each register
stored on the stack.
After the interrupt has been serviced/the Interrupt Service Routine (ISR) has been executed …
… the
registers
can be restored to its original status before the interrupt was detected // … the data can be
restored
from the stack
.
11(c) [3 marks]
mark per mark point (
Max 3
)
Pipelining adds an additional complexity // there could be a number of instructions still in the pipeline when the
interrupt is received
All the instructions currently in operation are usually discarded except for the last one/the one at write back
… the interrupt handler routine is applied to the remaining instruction.
Once the interrupt has been serviced the processor can restart with the next instruction in the sequence.
Max 3
)
Pipelining adds an additional complexity // there could be a number of instructions still in the pipeline when the
interrupt is received
All the instructions currently in operation are usually discarded except for the last one/the one at write back
… the interrupt handler routine is applied to the remaining instruction.
Once the interrupt has been serviced the processor can restart with the next instruction in the sequence.