4.1 CPU Architecture
AS Level · 22 questions found
What this topic covers
Section titled “What this topic covers”- Von Neumann model and stored program concept
- Special-purpose registers: PC, MDR, MAR, ACC, IX, CIR, Status Register
- ALU, Control Unit, system clock, Immediate Access Store (IAS)
- Address bus, data bus, control bus — data transfer between components
- Performance factors: cores, bus width, clock speed, cache memory
- Ports: USB, HDMI, VGA
- Fetch-Execute cycle and register transfer notation
- Interrupts: causes, ISR, when detected, how handled
Past paper questions
Section titled “Past paper questions”(a) The processor uses several registers, including the Accumulator (ACC) and the Current Instruction Register (CIR). 2 marks
Complete the table by describing the role of each register.
| Register | Role |
|---|---|
| ACC | |
| CIR |
(b) Increasing the number of cores in a processor can affect the performance of a computer. 2 marks
Describe the drawbacks of increasing the number of cores in a processor.
(c) State three differences between Dynamic RAM (DRAM) and Static RAM (SRAM). 3 marks
1
2
3
Show mark scheme
6(a) [2 marks]
1 mark for each correct description, max 2 marks Register Role stores the intermediate results of arithmetic and logical ACC operations // holds the result of a calculation CIR holds the instruction currently being decoded and/or executed
6(b) [2 marks]
1 mark per bullet point, max 2 marks e.g. • Latency may be increased • … because the cores must communicate with one another • There is a potential for dead-lock situations • … where one core may wait for information from other cores which in turn are waiting for the first one • Not all software is designed to use multi-cores • ... so some of the additional cores would be idle • Increased heat generation • ... which could cause damage to other components
6(c) [3 marks]
1 mark per bullet point, max 3 marks • DRAM requires to be refreshed/charged SRAM does not request a refresh • DRAM stores each bit as charge SRAM uses flip-flop to store each bit • DRAM is less expensive to manufacture SRAM is more expensive to manufacture • DRAM has slower access speeds SRAM has faster access times • DRAM has higher storage/bit/data density SRAM has lower storage/bit/data density • DRAM is used in main memory SRAM is used in cache
(a) (i) State what is meant by relative addressing. 1 mark
(ii) Registers such as the Accumulator (ACC) and the Index Register (IX) are used in the CPU. 2 marks
Identify two special purpose registers used in the CPU. Do not include the ACC or IX in your answers.
1
2
(b) The following table shows part of the instruction set for a processor. The processor has two registers: the ACC and an IX. 3 marks
| Instruction | Explanation | |
|---|---|---|
| Opcode | Operand | Operand |
| LDM | #n | Immediate addressing. Load the number n to ACC |
| LDD | Direct addressing. Load the contents of the location at the given address to ACC |
|
| LDI | Indirect addressing. The address to be used is at the given address. Load the contents of this second address to ACC |
|
| LDX | Indexed addressing. Form the address from + the contents of the index register. Copy the contents of this calculated address to ACC |
|
| LDR | #n | Immediate addressing. Load the number n to IX |
| can be an absolute or symbolic address # denotes a denary number, e.g. #127 |
can be an absolute or symbolic address # denotes a denary number, e.g. #127 |
can be an absolute or symbolic address # denotes a denary number, e.g. #127 |
The current contents of the main memory and the index register are shown.
Address Instruction
98 8
99 16
100 3
101 98
102 32
IX 2
Write the contents of the ACC after each instruction is executed.
| Instruction | Value in ACC |
|---|---|
| LDM #98 | |
| LDI 101 | |
| LDX 100 |
(c) A student buys a new computer. The table shows the specifications of the old computer and the new computer. 4 marks
| Old computer | New computer |
|---|---|
| 1.8 GHz dual core processor | 2.3 GHz dual core processor |
| 16 MB cache | 32 MB cache |
Explain why increasing the clock speed and increasing the cache memory will improve the performance of the computer.
Clock speed
Cache memory
Show mark scheme
3(a)(i) [1 mark]
1 mark • The value of the operand is an offset value which is added to another base value to give the address from which the contents are loaded to the accumulator
3(a)(ii) [2 marks]
1 mark per bullet point, max 2 marks • Program counter (PC) • Memory Data Register (MDR) • Memory Address Register (MAR) • Current Instruction Register (CIR) • Status Register
3(b) [3 marks]
1 mark for each correct value, max 3 marks Instruction Value in ACC LDM #98 98 LDI 101 8 LDX 100 32
3(c) [4 marks]
1 mark per bullet point, max 2 marks for each Clock Speed: • Processor can perform more F-E cycles per second • ... so more instructions / data can be processed each second Cache Memory: • Can store more of the most frequently used instructions • … which reduces the need to access slower RAM
A programmer is buying a new computer.
(a) The programmer is considering the following two computers:
| Computer 1 | Quad‑core 2.2 GHz processor 16‑bit architecture 1 GB Random Access Memory (RAM) 500 GB magnetic hard disk |
|---|---|
| Computer 2 | Dual‑core 3.8 GHz processor 32‑bit architecture 2 GB RAM 500 GB solid state drive (SSD) |
(i) Computer 1 has a magnetic hard disk. 4 marks
Complete the description of the principal operation of a magnetic hard disk by writing the missing words.
The magnetic hard disk has one or more ______ that can be
magnetised. These are mounted on a ______ and rotate at
high speed.
A ______ is moved across the surface on an arm.
When data is read, the changes in the ______ produce
a change in the electric current.
(ii) The two computers have different amounts of RAM. 3 marks
Explain how different amounts of RAM affect the performance of a computer.
(iii) The two computers have different bus widths. 2 marks
Explain how different bus widths affect the performance of a computer.
(b) Both computers have an Operating System (OS). 5 marks
Describe the purpose of an OS in a computer.
Show mark scheme
6(a)(i) [4 marks]
1 mark for each correctly completed space • platters • spindle • read/write head • magnetic field The magnetic hard disk has one or more platters that can be magnetised. These are mounted on a spindle and rotate at high speed. A read/write head is moved across the surface on an arm. When data is read the changes in the magnetic field produce a change in the electric current.
6(a)(ii) [3 marks]
1 mark each to max 3 • More RAM means more currently running data and instructions can be stored • without needing to use virtual memory • without having to fetch the data from secondary storage first • which has a slower access time • Less latency / delay waiting for instructions / data
6(a)(iii) [2 marks]
1 mark each to max 2 e.g. • Wider data bus means more data can be transferred between components at a time • there is less delay / latency when fetching data for a running process • Wider address bus means larger memory addresses can be used • allowing more memory locations to be accessed directly • so less likely to run out of memory
6(b) [5 marks]
1 mark each to max 5 e.g. • To provide a user interface • so that the user is able to communicate with the hardware • To manage memory • so that data can be stored and accessed • and multitasking is possible • To manage files • allowing the user to create, edit, update and delete files and folders • To manage inputs and outputs from hardware/peripherals • To handle processes • to make sure each process has fair access
(a) The table has six statements about the Von Neumann model for a computer system. 3 marks
Three of the statements are incorrect.
| Statement number | Statement |
|---|---|
| 1 | The Program Counter (PC) stores the next instruction to be fetched from memory. |
| 2 | The Arithmetic and Logic Unit (ALU) performs mathematical and logical operations. |
| 3 | The Control Unit (CU) sends signals to other components on the data bus. |
| 4 | The Memory Data Register (MDR) transfers data to the memory address stored in the Memory Address Register (MAR). |
| 5 | The MAR stores an address from memory. |
| 6 | The Accumulator (ACC) stores the result of calculations. |
Complete the table by writing the three incorrect statement numbers and the corrected statements.
| Incorrect statement number |
Corrected statement |
|---|---|
| ______ | ______ |
| ______ | ______ |
| ______ | ______ |
Show mark scheme
1(a) [3 marks]
1 mark for each correct row Incorrect Corrected statement statement number 1 The Program Counter (PC) stores the address of the next instruction to be fetched from memory. 3 The Control Unit (CU) sends signals to other components on the control bus. 4 The Memory Data Register (MDR) holds data to be stored in the memory address in the MAR. // The Memory Data Register (MDR) holds data read from the memory address in the MAR
1(b) [2 marks]
1 mark for name, 1 mark for corresponding role e.g. • Current Instruction Register // CIR • To store the instruction to be decoded / executed next • Status register // SR • To contain bits that can be referenced individually to indicate a state or event • Interrupt register • To store details of any interrupts that have occurred
1(c) [4 marks]
1 mark each to max 4 • At the start / end of FE cycle the interrupt register is checked • The priority of any interrupts waiting is checked • if the priority of the interrupt is higher than the current process • the contents of the registers are stored on the stack • The relevant Interrupt Service Routine (ISR) / interrupt handler is called to process the interrupt • When the ISR has finished, a further check is made for higher priority interrupts • if no more interrupts of higher priority, the register contents are restored and the next FE cycle continues
A computer has a processor.
Show mark scheme
2(a)(i) [2 marks]
1 mark each to max 2 - max 1 for each set of marks • The control unit synchronises the actions of the processor • by sending a command / signal on each timing signal produced by the system clock • using / along the control bus
2(a)(ii) [4 marks]
1 mark each • MAR [PC] and PC [PC] + 1 • MDR [[MAR]] • CIR [MDR] • Correct order • For example: • MAR [PC] • PC [PC] + 1 • MDR [[MAR]] • CIR [MDR]
2(b) [2 marks]
1 mark each • Using cache memory improves system performance • because cache is fast access memory close to the CPU • which stores frequently used instructions / data • so that they can be accessed faster than from RAM
2(c) [2 marks]
1 mark each to max 2 e.g. • HDMI transfers both audio and video using a single cable • HDMI has a high bandwidth • Data is transmitted in a stream • of uncompressed digital signals • HDMI uses a technology called Transition-Minimized Differential Signalling (TMDS)
A computer system has a dual-core Central Processing Unit (CPU).
(a) State the purpose of the system clock and the Control Unit (CU) in a CPU. 2 marks
System clock
CU
(b) (i) The number of cores in the processor affects the performance of the computer system. 2 marks
Identify one other feature of a processor that can affect the performance of a computer system and state why it affects the performance.
Feature
Reason
(ii) A solid state (flash) memory drive is automatically recognised by the computer when it is plugged into a port in the computer. 3 marks
Identify an appropriate type of port to connect the solid state memory drive to the computer.
Explain how this port provides an automatic connection.
Port
Explanation
Show mark scheme
3(a) [2 marks]
1 mark for system clock and 1 mark for Control Unit System clock • To synchronise operations • ... by creating and transmitting timing signals on the control bus Control Unit • Sends/receives control signals along control bus • Reads an instruction from the contents of the memory location whose address is stored in PC • Coordinates/synchronises the activity of other components in the CPU • Manages the execution of instructions • Controls communication between the components in the CPU
3(b)(i) [2 marks]
1 mark for the feature, 1 mark max for the matching reason e.g. Feature: clock speed • Higher clock speed means that more F-E cycles are executed per second // Higher clock speed results in more throughput Feature: bus width • Larger bus width means that more data transferred at the same time
3(b)(ii) [3 marks]
1 mark for correct port. 2 marks for explanation Port: USB / Universal Serial Bus Explanation: • A voltage change occurs when the drive is plugged in • The computer detects this voltage change • The code of the device is transferred to computer • … the OS finds the code of the device in the list of devices • … and loads the appropriate device driver
3(c) [2 marks]
1 mark for each bullet point ( max 2 ) e.g. • DRAM requires constant refresh cycles unlike SRAM • DRAM has lower access speed than SRAM
3(d)(i) [4 marks]
1 mark for each bullet point ( max 4 ) • The disc is spun at high speed • A laser is shone onto the disc to read / write • … using optical head to move it into position • … it follows the spiral track from the centre outwards • When writing the laser burns pits to represent the data • When reading the laser reflects from pits and lands • The reflection from a pit and a land is different • ... the differences are interpreted as 1 or 0
3(d)(ii) [3 marks]
1 mark for each bullet point ( max 3 ) The computer and optical disc reader/writer send and receive at different • speeds • A buffer allows temporary storage of the data • … so that the computer can transfer data to the buffer at the higher speed • ... and is not held up waiting for data to transfer // so the computer can carry on with other tasks • ... so the optical disc reader/writer is not overloaded • … and so that data is transferred to optical disc reader/writer from the buffer at the slower rate
A computer designed using the Von Neumann model for a computer system contains general purpose registers and special purpose registers.
(a) Describe the purpose of the Status Register (SR). 2 marks
(b) Identify two differences between general purpose registers and special purpose registers. 2 marks
1
2
Show mark scheme
8(a) [2 marks]
1 mark for each bullet point ( max 2 ) • To store the value of flags/bits • … that can be changed/set/cleared after arithmetic / logical operations • To allow flags to be checked • … to change instruction sequence
8(b) [2 marks]
1 mark for each bullet point ( max 2 ) • Special purpose registers have a specified role in the machine whereas general purpose registers can be used for all purposes defined by the programmer • Special purpose registers hold the state of the program’s execution while general purpose registers hold the program’s data during operations
The Central Processing Unit (CPU) of the basic Von Neumann model for a computer system contains several special purpose registers.
(a) The Memory Data Register (MDR), Index Register (IX) and the Accumulator (ACC) are examples of special purpose registers. 4 marks
Identify two other special purpose registers and state their role in the CPU.
Special purpose register 1
Role
Special purpose register 2
Role
(b) Describe what is meant by the Immediate Access Store (IAS) in a computer system. 2 marks
(c) A computer has a single 2.1 GHz CPU.
(i) Describe how increasing the clock speed to 4 GHz can increase the performance of the computer. 1 mark
(ii) A second computer has a CPU with two 2.1 GHz cores. 5 marks
Explain why the second computer does not always run twice as fast as the computer with one 2.1 GHz CPU.
Show mark scheme
5(a) [4 marks]
1 mark for identification of the register and 1 mark for role ( max 2 for each register) • Program Counter (PC) • stores the address where the next instruction is to be read from • Memory Address Register (MAR) • stores the address of the memory location (or an I/O component) currently being read from or written to • Current Instruction Register (CIR) • holds the instruction currently being decoded and/or executed • Status Register • Contains bits which can be referenced individually and set or cleared depending on the operation e.g. overflow, underflow
5(b) [2 marks]
1 mark for each bullet point ( max 2 ) • Immediate Access Store holds all the data / instructions / programs currently in use • Immediate Access Store is volatile memory • Immediate Access Store has fast access times
5(c)(i) [1 mark]
1 mark for each bullet point ( max 1 ) • The CPU can now perform nearly twice as many F-E cycles per second • Instead of 2.1 billion F-E cycles per second, the CPU can now perform 4 billion FE cycles per second
5(c)(ii) [5 marks]
1 mark for each bullet point ( max 5 ) • Multiple cores introduce additional overheads • …because of the need for communication between cores • Software may not be designed for multiple cores… • …so one of the cores will be left idle • Memory access speed may not match speed of cores… • …so causing delay • The two computers may have more differences than just the cores • …one may have more RAM which allows faster multitasking • ...one may have a GPU • ...etc.
A computer system is designed using the basic Von Neumann model.
Registers and buses are components in the Von Neumann model.
(a) (i) Identify three other components in the Von Neumann model of a computer system. 3 marks
Do not include registers or buses in your answers.
1
2
3
(ii) Identify two differences between special purpose registers and general purpose registers. 2 marks
1
2
(b) The following incomplete table contains steps of the Fetch‑Execute (F‑E) cycle and their descriptions. 4 marks
| Complete the table by writing the missin missing descriptions. | ng steps using register transfer notation and the |
|---|---|
| Step | Description |
| ______ | The address in PC is incremented. |
MDR [[MAR]] |
______ |
MAR [PC] |
______ |
| ______ | The contents of MDR are copied into CIR. |
(c) Interrupts can be caused by software programs or hardware devices. 1 mark
State one cause of a software interrupt.
(d) The following statements describe the stages that the CPU performs when an interrupt is detected. 3 marks
There are three missing statements.
Write the letter of the missing statements from the table in the correct place to complete the description.
1 At the end of each Fetch‑Execute (F‑E) cycle, the processor checks if an interrupt flag is set.
2
3 If the interrupt priority is high enough, the processor saves the current contents of the registers.
4
5 When servicing of the interrupt is complete, the processor restores the registers.
6
| Letter | Stage |
|---|---|
| A | The address of the Interrupt Service (ISR) handling routine is loaded into the Program Counter (PC). |
| B | Lower priority interrupts are re‑enabled. |
| C | The device causing the interrupt transfers data to the CPU. |
| D | The processor identifies the source of the interrupt and checks the priority of the interrupt. |
| E | The ISR is incremented. |
Show mark scheme
9(a)(i) [3 marks]
1 mark for each bullet point ( max 3 ). • Control unit (CU) • Arithmetic and Logic Unit (ALU) • Immediate Access Store (IAS) • (System clock)
9(a)(ii) [2 marks]
1 mark for each bullet point ( max 2 ). • Special purpose registers hold the status of a program whereas general purpose registers hold the temporary data while performing operations. • Special purpose registers are specialised for a specific use, whereas general purpose registers are used for any purpose. • General purpose registers can be used by most instructions, whereas special purpose can only be used by certain instruction
9(b) [4 marks]
1 mark for each correct answer (shaded cells) Step Description The address in PC is incremented. PC [PC] + 1 The data in the location pointed to by the MAR MDR [[MAR]] is copied to the MDR. The contents of PC are copied to the MAR. MAR [PC] The contents of MDR are copied into CIR. CIR [MDR]
9(c) [1 mark]
1 mark for an appropriate example. Examples: • Division by zero • Runtime error • Out of memory bounds • Program requesting an external device / input • Buffer overflow
9(d) [3 marks]
1 mark for each letter in the correct position (2, 4 and 6)
An interrupt is generated when a key is pressed on a computer keyboard.
Explain how the computer handles this interrupt. 5 marks
Show mark scheme
6 [5 marks]
1 mark each to max 5 An interrupt flag is raised in the (interrupt) register At the end of the current FE cycle // at the start of the next FE cycle The system checks the interrupt register for higher priority interrupts than current process If true, it stores the current contents of the registers on the stack The appropriate interrupt service routine (ISR) for the key press is called The input data from the keyboard is processed The contents of the registers are restored from the stack ... and control is passed back to previous process
A student has purchased a new laptop.
(a) The laptop is designed using the Von Neumann model for a computer system. 2 marks
Identify two types of signal that a control bus can transfer.
1
2
(b) Describe two ways the hardware of a laptop can be upgraded to improve the performance and explain how each upgrade improves the performance. 4 marks
1
2
(c) Peripherals are connected to the laptop using ports.
(i) A printer is connected to a Universal Serial Bus (USB) port. 1 mark
Describe how data is transmitted through a USB port.
(ii) A monitor is connected to the laptop using a different type of port. 1 mark
Identify one other type of port that can be used to connect the monitor.
(d) The laptop has systems software.
(i) Describe how the Operating System (OS) manages processes in the computer. 5 marks
(ii) Describe the purpose of utility software in a computer. 2 marks
Show mark scheme
5(a) [2 marks]
1 mark each to max 2 Examples: Interrupt Timing Read Write
5(b) [4 marks]
1 mark for description; 1 mark for corresponding explanation Examples Increase number of cores Each core can independently carry out a process at the same time // so that more instructions are performed in parallel Increase RAM capacity ... allowing more applications to reside in memory at the same time, saving disk access times Increase cache memory More data can be stored in fast access so less time is spent accessing from RAM Increase clock speed More Fetch-Decode-Execute (FDE) cycles can run each second / per unit time
5(c)(i) [1 mark]
1 mark for a correct answer 1 bit is transferred at a time Can be synchronous or asynchronous earlier versions are half-duplex USB-3 is full duplex and
5(c)(ii) [1 mark]
1 mark for identification of a suitable port Examples HDMI DisplayPort
5(d)(i) [5 marks]
1 mark each to max 5 Manages the scheduling of processes // decides which order to run processes Manages which resources the processes require … such as allocating memory Enables processes to share data Prevents interference between processes // resolution of conflicts Handles the process queue It allows multi-tasking / multi-processing ... by ensuring fair access, handling priorities and handling interrupts
5(d)(ii) [2 marks]
1 mark each to max 2 To help users to set-up / configure / analyse / optimise / maintain the computer ... ... by for example, making memory allocation more efficient ... by for example, checking the system for faults
A computer stores data in binary form.
(a) Draw one line from each description to its matching denary value.
Description Denary value
- 127
The smallest integer that can be represented in 8-bit two’s complement.
The largest integer that can be represented in 8-bit two’s complement.
The largest unsigned integer that can be represented in 8 bits.
(b) The computer has a Control Unit (CU), system clock and control bus. 3 marks 4 marks 2 marks
127
255
128
256
256
128
255 Explain how the CU, system clock and control bus operate to transfer data between the components of the computer system.
| Complete the table by writing the regist Fetch-Execute (F-E) cycle given in the table. | ter transfer notation for each stage of the |
|---|---|
| Stage description | Register transfer notation |
| The Program Counter (PC) is incremented | ______ |
| The data in the address stored in the Memory Address Register (MAR) is copied to the Memory Data Register (MDR) |
______ |
Show mark scheme
7(a) [4 marks]
1 mark for each correct line Description Denary value The smallest integer that can 127 be represented in 8-bit two's complement. 127 255 128 The largest integer that can be represented in 8-bit two's 256 complement. 256 128 The largest unsigned integer that can be represented in 8 255 bits.
7(b)
1 mark each to max 4 The system clock gives out timing signals … which are sent on the control bus …to synchronise the other system components The Control Unit initiates data transfer …by generating signals that are sent on the control bus to other components
7(c) [2 marks]
1 mark for each Register transfer notation Stage description Register transfer notation The Program Counter (PC) is PC [PC] + 1 incremented The data in the address stored in the MDR [[MAR]] Memory Address Register (MAR) is copied to the Memory Data Register (MDR)
(a) A greenhouse has an automatic window. 3 marks
| The window (X) op | perates according to the follow | wing criteria: | |
|---|---|---|---|
| Parameter | Description of parameter | Binary value | Condition |
| T | Temperature | 1 | Too high |
| T | Temperature | 0 | Acceptable |
| W | Wind speed | 1 | Too high |
| W | Wind speed | 0 | Acceptable |
| R | Rain | 1 | Detected |
| R | Rain | 0 | Not detected |
| M | Manual override | 1 | On |
| M | Manual override | 0 | Off |
The window opens ( X = 1) if:
the temperature is too high and the wind speed is acceptable
and
rain is not detected, or the manual override is off.
Draw a logic circuit to represent the operation of the window.
T
W
R
M
X
Show mark scheme
3(a) [3 marks]
1 mark for T AND NOT W 1 mark for NOT R OR NOT M 1 mark for final AND X
3(b) [2 marks]
1 mark for each set of rows as highlighted: 0 0 0 1 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 0
3(c) [2 marks]
1 mark for each bullet point: • to store data that does not change • data must be stored even when device is without power • to store boot up instructions / system software / firmware / BIOS
Draw one line from each Operating System (OS) management task to its most appropriate description.
OS Management task
hardware management
security management
memory management
process management
Description
dynamically allocates memory to processes
marks unallocated file storage for availability
installs programs for devices connected to external ports
validates user and process authenticity
allows processes to transfer data to and from each other 4 marks
Show mark scheme
3 [4 marks]
1 mark for each correct line: OS Management task Description dynamically allocates memory to processes hardware management marks unallocated file storage for availability security management installs programs for devices connected to external ports memory management validates user and process authenticity process management allows processes to transfer data to and from each other
(a) A computer system is designed using the basic Von Neumann model.
(i) Describe the role of the registers in the Fetch-Execute (F-E) cycle. 5 marks
(ii) Describe when interrupts are detected in the F-E cycle and how the interrupts are handled. 5 marks
Detected
Handled
(b) Identify one factor that can affect the performance of the computer system and state how it impacts the performance. 2 marks
Factor
Impact Question 6 continues on the next page.
(c) The table shows part of the instruction set for a processor. The processor has one general purpose register, the Accumulator (ACC).
| Instruction | Explanation | |
|---|---|---|
| Opcode | Operand | Operand |
AND |
#n |
Bitwise AND operation of the contents of ACC with the operand |
XOR |
#n |
Bitwise XOR operation of the contents of ACC with the operand |
OR |
#n |
Bitwise OR operation of the contents of ACC with the operand |
LSL |
#n |
Bits in ACC are shifted logically n places to the left. Zeros are introduced on the right hand end |
LSR |
#n |
Bits in ACC are shifted logically n places to the right. Zeros are introduced on the left hand end |
| # denotes a denary number, e.g. #123 | # denotes a denary number, e.g. #123 | # denotes a denary number, e.g. #123 |
(i) Complete the register to show the result after the instruction AND #2 is executed. 1 mark
Register before: 0 1 1 0 1 1 0 1
Register after:
(ii) Complete the register to show the result after the instruction OR #8 is executed. 1 mark
Register before: 0 1 1 0 1 1 0 1
Register after:
(iii) Complete the register to show the result after the operation LSL #4 is executed. 1 mark
Register before: 0 1 1 0 1 1 0 1
Register after:
Show mark scheme
6(a)(i) [5 marks]
1 mark per bullet point to max 5 The Program Counter (PC) holds the address of the next instruction … …and the contents are incremented / changed to the next address each cycle The Memory Address Register (MAR) holds the address to fetch the data (from the PC) The Memory Data Register (MDR) holds the data at the address in MAR The instruction is transferred to Current Instruction Register (CIR) for decoding and execution
6(a)(ii) [5 marks]
1 mark for detection At the start/end of a FE cycle 1 mark for handling to max 4 Priority is checked If lower priority than current process continue with F-E cycle If higher priority than current process … … state of current process is / registers are stored on stack Location / type of interrupt identified... …appropriate ISR is called to handle the interrupt When ISR finished, check for further interrupts (of high priority) / return to step 1 Otherwise load data from stack and continue with process
6(b) [2 marks]
1 mark for factor 1 mark for impact e.g. Clock speed… …higher clock speed means more FE cycles per second Number of cores… …means more instructions can be carried out simultaneously Bus width … …allows the transfer of more data each time // allows more memory locations to be directly accessed Cache … … the higher capacity the more frequently used instructions it can store for fast access
6(c)(i) [1 mark]
0000 0000
6(c)(ii) [1 mark]
0110 1101
6(c)(iii) [1 mark]
1101 0000
(a) The Fetch-Execute (F-E) cycle is represented in register transfer notation. 3 marks
Describe each of the given steps.
| Step | Description |
|---|---|
PC[PC] + 1 |
______ |
MDR[[MAR]] |
______ |
MAR[PC] |
______ |
(b) Explain how interrupts are handled during the F-E cycle. 5 marks
Show mark scheme
2(a) [3 marks]
1 mark for each correct description Step Description Address in PC is incremented PC [PC] + 1 The data in the address held in the MAR is copied MDR [[MAR]] to the MDR The contents of the PC are copied to the MAR MAR [PC]
2(b) [5 marks]
1 mark per point to max 5 Check for interrupt at start/end of an F-E cycle Priority is checked If lower priority than current process continue with F-E cycle If higher priority than current process … … state of current process is / registers are stored on stack Location/type of interrupt identified Appropriate ISR is called to handle the interrupt When ISR finished, check for further interrupts (of higher priority) / return to step 1 Otherwise load data from stack and continue with next F-E cycle (of process)
(a) There are two errors in the following register transfer notation for the fetch‑execute cycle. 4 marks
1 MAR [PC]
2 PC [PC] − 1
3 MDR [MAR]
4 CIR [MDR]
Complete the following table by:
identifying the line number of each error
describing the error
writing the correct statement.
Line
numberDescription of the error Correct statement
(b) The following table shows part of the instruction set for a processor. The processor has one general purpose register, the Accumulator (ACC), and an Index Register (IX). 4 marks
| Instruction | Explanation | |
|---|---|---|
| Opcode | Operand | Operand |
LDM |
#n |
Immediate addressing. Load the number n to ACC |
LDD |
<address> |
Direct addressing. Load the contents of the location at the given address to ACC |
STO |
<address> |
Store the contents of ACC at the given address |
INC |
<register> |
Add 1 to the contents of the register (ACC or IX) |
CMP |
<address> |
Compare the contents of ACC with the contents of |
JPN |
<address> |
Following a compare instruction, jump to if the compare was False |
JMP |
<address> |
Jump to the given address |
IN |
Key in a character and store its ASCII value in ACC | |
OUT |
Output to the screen the character whose ASCII value is stored in ACC | |
END |
Return control to the operating system | |
XOR |
#n |
Bitwise XOR operation of the contents of ACC with the operand |
XOR |
<address> |
Bitwise XOR operation of the contents of ACC with the contents of |
AND |
#n |
Bitwise AND operation of the contents of ACC with the operand |
AND |
<address> |
Bitwise AND operation of the contents of ACC with the contents of |
OR |
#n |
Bitwise OR operation of the contents of ACC with the operand |
OR |
<address> |
Bitwise OR operation of the contents of ACC with the contents of |
LSL |
#n |
Bits in ACC are shifted logically n places to the left. Zeros are introduced on the right hand end |
LSR |
#n |
Bits in ACC are shifted logically n places to the right. Zeros are introduced on the left hand end |
| can be an absolute or symbolic address # denotes a denary number, e.g. #123 B denotes a binary number, e.g. B01001101 |
can be an absolute or symbolic address # denotes a denary number, e.g. #123 B denotes a binary number, e.g. B01001101 |
can be an absolute or symbolic address # denotes a denary number, e.g. #123 B denotes a binary number, e.g. B01001101 |
The current contents of main memory are shown:
Address Data
100 00001111
101 11110000
102 01010101
103 11111111
104 00000000
Each row of the following table shows the current contents of ACC in binary and the instruction that will be performed on those contents.
| Complete the table by w instruction. | writing the new contents of the A | ACC after the execution of each |
|---|---|---|
| Current contents of the ACC | Instruction | New contents of the ACC |
11111111 |
OR 101 |
|
00000000 |
XOR #15 |
|
10101010 |
LSR #2 |
|
01010101 |
AND 104 |
Show mark scheme
6(a) [4 marks]
1 mark for identification of line and description of error 1 mark for the correct statement Line Description of the error Correct statement number 2 Program Counter should be incremented, ← PC [PC] + 1 not decremented 3 It should be the contents of the address in ← MDR [[MAR]] the MAR
6(b) [2 marks]
1 mark for each correct row Current contents of the ACC Instruction New contents of the ACC 11111111 OR 101 11111111 00000000 XOR #15 00001111 10101010 LSR #2 00101010 01010101 AND 104 00000000
The Von Neumann model for a computer system uses registers.
(a) Describe the role of the following special purpose registers in the fetch-execute (F-E) cycle.
(i) Memory Address Register (MAR) 4 marks
Memory Data Register (MDR)
(ii) Another special purpose register is the Index Register. 1 mark
Identify one other special purpose register used in the Von Neumann model for a computer system.
(b) The following table shows part of the instruction set for a processor. The processor has one general purpose register, the Accumulator (ACC), and an Index Register (IX).
| Instruction | Explanation | |
|---|---|---|
| Opcode | Operand | Operand |
LDM |
#n |
Immediate addressing. Load the number n to ACC |
LDD |
<address> |
Direct addressing. Load the contents of the location at the given address to ACC |
STO |
<address> |
Store the contents of ACC at the given address |
INC |
<register> |
Add 1 to the contents of the register (ACC or IX) |
CMP |
<address> |
Compare the contents of ACC with the contents of |
JPN |
<address> |
Following a compare instruction, jump to if the compare was False |
JMP |
<address> |
Jump to the given address |
IN |
Key in a character and store its ASCII value in ACC | |
OUT |
Output to the screen the character whose ASCII value is stored in ACC | |
END |
Return control to the operating system | |
XOR |
#n |
Bitwise XOR operation of the contents of ACC with the operand |
XOR |
<address> |
Bitwise XOR operation of the contents of ACC with the contents of |
OR |
#n |
Bitwise OR operation of the contents of ACC with the operand |
OR |
<address> |
Bitwise OR operation of the contents of ACC with the contents of |
AND |
#n |
Bitwise AND operation of the contents of ACC with the operand |
AND |
<address> |
Bitwise AND operation of the contents of ACC with the contents of |
LSL |
#n |
Bits in ACC are shifted logically n places to the left. Zeros are introduced on the right hand end |
LSR |
#n |
Bits in ACC are shifted logically n places to the right. Zeros are introduced on the left hand end |
| can be an absolute or symbolic address # denotes a denary number, e.g. #123 |
can be an absolute or symbolic address # denotes a denary number, e.g. #123 |
can be an absolute or symbolic address # denotes a denary number, e.g. #123 |
The current contents of main memory are shown:
Address Data
100 01010101
101 11110000
102 00001111
103 00000000
104 11111111
(i) In the following table, each row shows the current contents of the ACC in binary and the instruction that will be performed on those contents. 4 marks
| Complete the table instruction. | by writing the new contents of the | e ACC after the execution of each |
|---|---|---|
| Current contents of the ACC | Instruction | New contents of the ACC |
01010101 |
XOR 101 |
|
11110000 |
AND 104 |
|
00001111 |
LSL #4 |
|
11111111 |
OR 102 |
(ii) The following table contains five assembly language instruction groups. 4 marks
Write an appropriate assembly language instruction for each instruction group, using the given instruction set. The first one has been completed for you.
| Instruction Group | Instruction |
|---|---|
| Data movement | LDM #2 |
| Input and output of data | |
| Arithmetic operations | |
| Unconditional and conditional instructions | |
| Compare instructions |
(iii) The opcode LDM uses immediate addressing. The opcode LDD uses direct addressing. 2 marks
Identify and describe one additional mode of addressing.
Mode of addressing
Description
Show mark scheme
8(a)(i) [1 mark]
1 mark for each bullet point to max 2 for each register MAR Stores the next address to be fetched • ... held in the Program Counter (PC) • The data at this address is then fetched • MDR Stores the data from the address pointed to by the MAR • The data in it is copied to the Current Instruction Register (CIR) •
8(a)(ii)
1 mark for a correct register e.g. Program Counter (PC) Current Instruction Register (CIR) Status register Interrupt register
8(b)(i) [4 marks]
1 mark for each correct answer Current contents of New contents of Instruction the ACC the ACC 01010101 XOR 101 1010 0101 11110000 AND 104 1111 0000 00001111 LSL #4 1111 0000 11111111 OR 102 1111 1111
8(b)(ii) [4 marks]
1 mark for each correct instruction Instruction Group Instruction Data movement LDM #2 Input and output of data IN / OUT Arithmetic Operations INC ACC / INC IX Unconditional and conditional instructions JPN 100 / JMP 100 Compare instructions CMP 100
8(b)(iii) [2 marks]
1 mark for name, 1 mark for description Indirect addressing • the address to be used is at the given address • Relative addressing • the address to be used is an offset number of locations away, relative to • the address of the current instruction Indexed addressing • form the address from the given address plus the contents of the index • register
(a) There are two errors in the following register transfer notation for the fetch‑execute cycle. 4 marks
1 MAR [PC]
2 PC [PC] − 1
3 MDR [MAR]
4 CIR [MDR]
Complete the following table by:
identifying the line number of each error
describing the error
writing the correct statement.
Line
numberDescription of the error Correct statement
(b) The following table shows part of the instruction set for a processor. The processor has one general purpose register, the Accumulator (ACC), and an Index Register (IX). 4 marks
| Instruction | Explanation | |
|---|---|---|
| Opcode | Operand | Operand |
LDM |
#n |
Immediate addressing. Load the number n to ACC |
LDD |
<address> |
Direct addressing. Load the contents of the location at the given address to ACC |
STO |
<address> |
Store the contents of ACC at the given address |
INC |
<register> |
Add 1 to the contents of the register (ACC or IX) |
CMP |
<address> |
Compare the contents of ACC with the contents of |
JPN |
<address> |
Following a compare instruction, jump to if the compare was False |
JMP |
<address> |
Jump to the given address |
IN |
Key in a character and store its ASCII value in ACC | |
OUT |
Output to the screen the character whose ASCII value is stored in ACC | |
END |
Return control to the operating system | |
XOR |
#n |
Bitwise XOR operation of the contents of ACC with the operand |
XOR |
<address> |
Bitwise XOR operation of the contents of ACC with the contents of |
AND |
#n |
Bitwise AND operation of the contents of ACC with the operand |
AND |
<address> |
Bitwise AND operation of the contents of ACC with the contents of |
OR |
#n |
Bitwise OR operation of the contents of ACC with the operand |
OR |
<address> |
Bitwise OR operation of the contents of ACC with the contents of |
LSL |
#n |
Bits in ACC are shifted logically n places to the left. Zeros are introduced on the right hand end |
LSR |
#n |
Bits in ACC are shifted logically n places to the right. Zeros are introduced on the left hand end |
| can be an absolute or symbolic address # denotes a denary number, e.g. #123 B denotes a binary number, e.g. B01001101 |
can be an absolute or symbolic address # denotes a denary number, e.g. #123 B denotes a binary number, e.g. B01001101 |
can be an absolute or symbolic address # denotes a denary number, e.g. #123 B denotes a binary number, e.g. B01001101 |
The current contents of main memory are shown:
Address Data
100 00001111
101 11110000
102 01010101
103 11111111
104 00000000
Each row of the following table shows the current contents of ACC in binary and the instruction that will be performed on those contents.
| Complete the table by w instruction. | writing the new contents of the A | ACC after the execution of each |
|---|---|---|
| Current contents of the ACC | Instruction | New contents of the ACC |
11111111 |
OR 101 |
|
00000000 |
XOR #15 |
|
10101010 |
LSR #2 |
|
01010101 |
AND 104 |
Show mark scheme
6(a) [4 marks]
1 mark for identification of line and description of error 1 mark for the correct statement Line Description of the error Correct statement number 2 Program Counter should be incremented, ← PC [PC] + 1 not decremented 3 It should be the contents of the address in ← MDR [[MAR]] the MAR
6(b) [2 marks]
1 mark for each correct row Current contents of the ACC Instruction New contents of the ACC 11111111 OR 101 11111111 00000000 XOR #15 00001111 10101010 LSR #2 00101010 01010101 AND 104 00000000
A processor has one general purpose register, the Accumulator (ACC), and several special purpose registers.
(a) Complete the following description of the role of the registers in the fetch-execute cycle by writing the missing registers. 5 marks
The ______ holds the address of the next instruction
to be loaded. This address is sent to the ______ .
The ______ holds the data fetched from this address.
This data is sent to the ______ and the Control Unit
decodes the instruction’s opcode.
The ______ is incremented.
Show mark scheme
3(a)
1 mark for each completed statement The Program Counter holds the address of the next instruction to be loaded. This address is sent to the Memory Address Register . The Memory Data Register holds the data fetched from this address. This data is sent to the Current Instruction Register and the Control Unit decodes the instruction’s opcode. The Program Counter is incremented.
3(b) [6 marks]
1 mark for each shaded set of values Memory address Instruction ACC IX Output address 365 366 367 368 1 3 65 66 0 200 1 201 202 203 2 204 2 205 2 206 65 207 A 208 200 2 201 202 203 3 204 3 205 3 206 66 207 B 208 200 3 201 202 209
3(c)(i) [1 mark]
1 1 0 1 0 1 0 0
3(c)(ii) [1 mark]
1 mark for correct answer The number is divided by 8 (and only whole number retained)
Seth uses a computer for work.
(a) Complete the following descriptions of internal components of a computer by writing the missing terms. 5 marks
The ______ transmits the signals to coordinate events based
on the electronic pulses of the ______ .
The ______ carries data to the components, while the
______ carries the address where data needs to be written to
or read from.
The ______ performs mathematical operations and
logical comparisons.
(b) Describe the ways in which the following factors can affect the performance of his laptop computer. 4 marks
Number of cores
Clock speed
(c) Seth accesses both software and data using cloud computing.
(i) Give two benefits of storing data using cloud computing. 2 marks
1
2
(ii) Give two drawbacks of Seth using cloud computing. 2 marks
1
2
(d) Draw one line from each term to its most appropriate description. 4 marks
Term Description
It is only visible to devices within the Local Area Network (LAN)
Public IP address
Private IP address
Dynamic IP address
Static IP address
It increments by 1 each time the device connects to the internet
A new one is reallocated each time a device connects to the internet
It can only be allocated to a router
It is visible to any device on the internet
It does not change each time a device connects to the internet
Show mark scheme
5(a)
1 mark for each term correctly inserted The control unit/bus transmits the signals to coordinate events based on the pulses of the ( system) clock . The data bus carries data to components, while the address bus carries the address where data is being written to or read from. The arithmetic logic unit/ALU performs mathematical operations and logical comparisons.
5(b) [4 marks]
1 mark per bullet point to max 3 per factor. max 4 overall. Number of cores: Each core processes one instruction per clock pulse • More/multiple cores mean that sequences of instructions can be split • between them … and so more than one instruction is executed per clock pulse // more • sequences of instructions can be run at the same time More cores decreases the time taken to complete task • Clock speed: Each instruction is executed on a clock pulse // one F-E cycle is run on • each clock pulse ... so the clock speed dictates the number of instructions that can be run • per second The faster the clock speed the more instructions can be run per second •
5(c)(i) [2 marks]
1 mark per bullet point to max 2 Cloud storage can be free (for small quantities ) • No need for separate (high capacity) storage devices // saves storage on • existing devices Can access data from any computer with internet access • Most cloud data services will have in-built backup/disaster recovery • Security could be better • Can easily increase capacity • Data can be easily shared •
5(c)(ii) [4 marks]
1 mark per bullet point to max 2 : Can only access (the cloud) with internet access • Security may not be strong // no control over security • There may not be any backups // no control over backups • It can take a long time to upload/download the data • It can be more expensive in the long term • There could be a limit to the amount of storage unless paid for • There could be compatibility/access issues • There could be issues with the company offering cloud services •
5(d)
1 mark for each correct line
A processor has one general purpose register, the Accumulator (ACC), and several special purpose registers.
(a) Complete the following description of the role of the registers in the fetch-execute cycle by writing the missing registers. 5 marks
The ______ holds the address of the next instruction
to be loaded. This address is sent to the ______ .
The ______ holds the data fetched from this address.
This data is sent to the ______ and the Control Unit
decodes the instruction’s opcode.
The ______ is incremented.
Show mark scheme
3(a)
1 mark for each completed statement The Program Counter holds the address of the next instruction to be loaded. This address is sent to the Memory Address Register . The Memory Data Register holds the data fetched from this address. This data is sent to the Current Instruction Register and the Control Unit decodes the instruction’s opcode. The Program Counter is incremented.
3(b) [6 marks]
1 mark for each shaded set of values Memory address Instruction ACC IX Output address 365 366 367 368 1 3 65 66 0 200 1 201 202 203 2 204 2 205 2 206 65 207 A 208 200 2 201 202 203 3 204 3 205 3 206 66 207 B 208 200 3 201 202 209
3(c)(i) [1 mark]
1 1 0 1 0 1 0 0
3(c)(ii) [1 mark]
1 mark for correct answer The number is divided by 8 (and only whole number retained)